UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ https://uvvm.github.io/
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_supplementary_doc Updated to UVVM v2 2025.09.17 - Please see CHANGES.TXT for details. 2025-09-17 10:03:45 +02:00
bitvis_irqc Updated to UVVM v2 2026.02.14 - Please see CHANGES.TXT for details 2026-02-14 11:36:01 +01:00
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bitvis_vip_clock_generator Updated to UVVM v2 2026.02.14 - Please see CHANGES.TXT for details 2026-02-14 11:36:01 +01:00
bitvis_vip_error_injection Updated to UVVM v2 2026.02.14 - Please see CHANGES.TXT for details 2026-02-14 11:36:01 +01:00
bitvis_vip_ethernet Updated to UVVM v2 2026.02.14 - Please see CHANGES.TXT for details 2026-02-14 11:36:01 +01:00
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LICENSE Ran license_change_util.pl on this repository (from mk_perl_utils repository) 2020-03-02 12:45:21 +01:00
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UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches.

Overview, Readability, Maintainability, Extensibility and Reuse are all vital for FPGA development efficiency and quality. UVVM VVC (VHDL Verification Component) Framework was released in 2016 to handle exactly these aspects.

UVVM consists currently of the following elements:

For information on how to get started, see Getting Started.

For frequently asked questions, see FAQ.

The complete UVVM documentation can be found on https://uvvm.github.io.